Fadal 1420-1 Video Card Reverse Engineering and Schematic

This article originally appeared in My little (home) shop thread on Practical Machinist.

I finished my reverse engineered schematic of the Fadal 1420-1 video board. I’d estimate I have 20-25 hours into the schematic at this point.

The schematic, and observation of the control display, lead to some interesting observations about the original design.

It’s widely told that Adrian de Caussin is the one who designed the control hardware, unfortunately he passed away some time ago (a reference from 1996 indicates he’d passed by then), so this public accounting may be the only hardware level details known outside of the de Caussin family.

I did reach out to David de Caussin the younger to try and learn details about the original control development, because at this point they are considered vintage computer systems. Unfortunately I didn’t receive a reply from him, so I had to go at it myself.

Up to this point I had dumped the character generator ROM, as seen in a previous post. This lead to some curious questions which I believe are answered by the schematic diagram, namely why each character is represented by 16 lines, but the latter 8 lines are blank?

Well, let’s start with some simple things we can observe about the video display:

First, the display is 64 columns by 16 rows. My research indicates this was a common format for S100 computers around the time the Fadal control was created. It makes sense then that the Fadal control would leverage some existing standards, but why roll their own video card instead of buying one or copying an existing design?

The second observation may give that answer. When the control goes into a mode where the axes are moving and the DRO display is active, it switches the top 6 lines of the screen into a doublewide mode. The top 6 lines become 32 columns wide and the characters become square. This is to aid in viewing the DRO output during operation. I presume the top 6 lines were chosen because the control is 5 axis capable, so 1 line per axis and then a blank line to separate the DRO from the scrolling portion of the display.

The third observation we can make is that the screen seems to flicker at times when the cursor is blinking, or the display is scrolling. This is answered too by the schematic.

So, let’s discuss some of the components of the video card and why it’s unique. I’ll just get the unique part out first: the video card is implemented entirely in discrete logic. This is like using a bunch of small PLCs or relay logic to implement something complex instead of an integrated control. Many video cards of the era were built around CRTC (CRT Controllers), such as the Motorola 6845, which was common in the IBM PC video cards.

Fadal generated the video with a bunch of 4 bit counters, a standalone 3.4992Mhz dot clock, and a shift register that is fed by the output of the character ROM.

The 64×16 display area is stored in a pair 2114 1Kx4 static RAMs, giving a total of 1KB of video RAM. This hints at why the screen has noise artifacts. The video generator circuitry is constantly running, generating a video display while the machine is turned on. The main CPU of the control needs to write characters to the video memory and copy the contents when the screen scrolls. The cursor is implemented by a routine that blinks the < on and off by updating video memory.

When you have a CPU that needs to read/write to memory and a video generator that needs to read the memory, there becomes a conflict. You could eliminate the conflict by signalling the CPU that the video display is during the vertical retrace (vertical sync) and only write to the RAM then, however this is not how Fadal did it. Video cards based on the 6845 can signal this vertical sync to the CPU, but the Fadal card simply allows the CPU to step on the video generator. That is, the CPU asserts control of the video memory, does its read/write, then deasserts control, allowing the video generator to read the video memory and render the screen. It’s this heavy handed control of the video memory that results in the visual artifacts when the cursor blinks or the screen is updated.

Looking at pictures of the later board revisions, they implemented a dual ported 1KB video RAM. This allowed the CPU to write to addresses arbitrarily and the video generator to read from the memory without any contention. The end result is that Fadal 1420-2 video card does not have the visual artifacts because the video generator can read the video memory while the CPU is writing and reading it. This point may seem rather minor to some, but for customers that paid the price of a small house in the 80’s, it was a subtle, but welcomed improvement. The video generator circuitry is really rather simple. The 3.4992Mhz clock is piped into a latch that selects between the original frequency, or half that frequency (more on that later). Then the clock goes to an 8 bit shift register, which is loaded with each line of the character bitmap from the char EPROM. The shift register shuffles bits via an invertor directly to the output driver chip, which then controls a 2N3904 transistor and some resistors make an NTSC compatible video output. There is other logic to generate the sync signals, but the basic pixel pipeline is short and simple. The main clock also drives several counters which control the address lines of the video ram, stepping through all of the character locations. This gets somewhat complicated because of the next feature.

The doublewide DRO feature of the video card is actually what is novel and uses up a significant portion of the logic on the board. If all you had to do was step through 1KB of ram and generate video lines, it could be probably half the chip count. The doublewide feature is enable by writing to the I/O port allocated to the video card. That I/O port is shared between the option bits (J2 where you specify baud rates and line voltage) and the double wide mode. In conjunction with a write to I/O port 32, the data line DO1 determines if doublewide mode is on or off. When a read from I/O port 32 is done, you get all the option bits. The Fadal control has the ability to set many of the critical hard power-on options in dip switches or jumpers. Specifically the backlash is settable in dip switches on the axis drive boards and the basic option bits are set on the video card. These settings are all adjustable via BL or SETP commands anyway, overriding the settings in the hardware.

The doublewide mode is generated by keeping each pixel on for twice the time, by using a video clock that runs at half speed. This results in overscanning the characters from the first 32 columns of the display, creating a more legible font.

So, to summarize, the Fadal 1420-1 video card was a clever piece of engineering, the primary complexity was driven by the need for a doublewide mode on the first 6 lines of the display and this is why Fadal didn’t use an off-the-shelf card or copy and existing card.

The 6845 CRTC doesn’t offer a double-wide mode either, but it offers other capabilities. I think that since the roots of the Fadal control were based on hardware they were already familiar with, the Altair 8080 S100 bus computer, they decided to stick to the late 70’s tech instead of embracing the early 80’s tech that existed at the time.

The IBM MDA Monochrome Display Adaptor used the 6845 CRTC, had 4KB of 2114 based static ram, and about 30% higher chip count, not to mention it was more expensive, by BOM standards. I think Fadal made the choices they did based on cost, owning the design, simplicity, and ease of manufacture. The board is a mix and match of 74 series TTL logic, with only a small number of costly components (RAM, EPROM, and Intel specific S100 bus interface chips).

Fadal 1420-1 Video board schematic

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